From c907d3613f29ff11c83f93a8c095ab5c8d6f5901 Mon Sep 17 00:00:00 2001
From: Nikhil Parasaram <tommycjniko@gmail.com>
Date: Tue, 5 Mar 2019 18:56:01 +0530
Subject: [PATCH] Fix edge case for the memory access

---
 mythril/laser/ethereum/state/memory.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mythril/laser/ethereum/state/memory.py b/mythril/laser/ethereum/state/memory.py
index 0bb4fa94..085a7ec8 100644
--- a/mythril/laser/ethereum/state/memory.py
+++ b/mythril/laser/ethereum/state/memory.py
@@ -152,7 +152,7 @@ class Memory:
                 self[start + i] = cast(List[Union[int, BitVec]], value)[i]
 
         else:
-            if key > self.__len__():
+            if key >= self.__len__():
                 return
             if isinstance(value, int):
                 assert 0 <= value <= 0xFF