Fix edge case for the memory access

6 years ago · c907d3613f
parent 1da86af5d8
commit c907d3613f
1 changed files with 1 additions and 1 deletions
--- a/mythril/laser/ethereum/state/memory.py
+++ b/mythril/laser/ethereum/state/memory.py
@ -152,7 +152,7 @@ class Memory:
                self[start + i] = cast(List[Union[int, BitVec]], value)[i]

        else:
-            if key > self.__len__():
+            if key >= self.__len__():
                return
            if isinstance(value, int):
                assert 0 <= value <= 0xFF